The present invention relates generally to a configurable phase locked loop (PLL) architecture, and more particularly to an apparatus and method for using a PLL having various combinations of phase and frequency detectors and feedback loops.
A PLL is a feedback control system for automatically adjusting the phase and/or frequency of a locally generated signal to match the phase (and/or frequency) of an input signal. A typical PLL has three components: a detector for discerning a difference in phase and/or frequency between the local feedback signal and the input signal; a filter for filtering unwanted harmonics or frequencies from the detector output; and a voltage controlled oscillator (VCO). The output of the VCO provides the local.feedback signal. The detector will xe2x80x9clockxe2x80x9d the output frequency of the VCO to the frequency of the input signal by causing the VCO to correct itself.
Some conventional PLL circuits either use a combination of a phase-frequency detector (PFD) and a phase detector (PD), or a combination of a bang-bang PFD and a phase detector (PD) for clock and data recovery applications. However, even these PLL architectures provide limited configuration options. For instance, clock and data recovery applications are limited to an operation in which the PLL achieves lock first using a PFD, and then uses a PD for actual clock and data recovery. Conventional dual loop architectures present limited options in the loop designs and not flexible to suit different applications needed in clock recovery and synthesis. Employing multiple PLL circuits to accomplish many different applications consumes critical space on a semiconductor device.